Extremely low voltage and high speed deep trapping MONOS memory with good retention

Albert Chin*, C. H. Lai, H. J. Yang, W. J. Chen, Y. H. Wu, H. L. Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We propose and demonstrate a novel low voltage and high speed MONOS non-volatile memory (NVM) using deep trapping layer, metal-gate and high-K dielectric technology. Low 13 V program/erase (P/E), fast 100 μs speed, large 1.9 V extrapolated 10-year memory window at 85°C, and small 21% degradation after 85°C 10k cycling are simultaneously measured in SiO 2/AlN/AlHfO/Ir-Oxide MONOS memory. Even lower 8 V (or ± 4V) P/E, fast 100 μs speed, still large 1.45 V extrapolated 10-year memory window at 85°C, and small 16% degradation after 85°C 10k cycling are measured in SiO2/HfON/HfAlO/TaN MONOS device. This is the reported lowest P/E voltage and fastest speed NVM to date and useful for embedded SoC under 5 V.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
PublisherIEEE Computer Society
Pages744-747
Number of pages4
ISBN (Print)1424401615, 9781424401611
DOIs
StatePublished - 1 Jan 2006
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 23 Oct 200626 Oct 2006

Publication series

NameICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

ConferenceICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period23/10/0626/10/06

Fingerprint Dive into the research topics of 'Extremely low voltage and high speed deep trapping MONOS memory with good retention'. Together they form a unique fingerprint.

Cite this