In order to extend the Moore's law, the interests have been devoted to several different areas, such as the use of strained technology, the high-k/metal-gate, high mobility channel materials etc. Among these efforts, strained technology seems to be the most successful one for its development over several generations and more Moore becomes the most recent interest. However, the reliability and variability become a great concern. In this paper, we will first give an overview on the strain-silicon technology, such as eSiGe, eSi:C, stress memorization technique (SMT), dual stress liners (DSL), and replacement high-k/metal-gate (RMG) process, after the 90nm CMOS generation. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be outlined. Then, the variability of the strained CMOS devices with focus on the experimental discrete dopant profiling will be demonstrated. Finally, the strategies and challenges of strained-silicon devices on advanced 3D device structure and IC will be discussed.