Extension of Moore's law via strained technologies- the strategies and challenges

Steve S. Chung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In order to extend the Moore's law, the interests have been devoted to several different areas, such as the use of strained technology, the high-k/metal-gate, high mobility channel materials etc. Among these efforts, strained technology seems to be the most successful one for its development over several generations and more Moore becomes the most recent interest. However, the reliability and variability become a great concern. In this paper, we will first give an overview on the strain-silicon technology, such as eSiGe, eSi:C, stress memorization technique (SMT), dual stress liners (DSL), and replacement high-k/metal-gate (RMG) process, after the 90nm CMOS generation. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be outlined. Then, the variability of the strained CMOS devices with focus on the experimental discrete dopant profiling will be demonstrated. Finally, the strategies and challenges of strained-silicon devices on advanced 3D device structure and IC will be discussed.

Original languageEnglish
Title of host publicationULSI Process Integration 7
Pages27-41
Number of pages15
Edition7
DOIs
StatePublished - 1 Dec 2011
Event7th Symposium on ULSI Process Integration - 220th ECS Meeting - Boston, MA, United States
Duration: 9 Oct 201114 Oct 2011

Publication series

NameECS Transactions
Number7
Volume41
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

Conference7th Symposium on ULSI Process Integration - 220th ECS Meeting
CountryUnited States
CityBoston, MA
Period9/10/1114/10/11

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