Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement

Po Hsun Wu, Po-Hung Lin, Tung Chieh Chen, Ching Feng Yeh, Tsung Yi Ho, Bin Da Liu

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. To simultaneously consider symmetry, wirelength, area utilization, and current/signal paths during analog placement, this paper explores the feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement optimization. Experimental results show that the proposed formulation and algorithms can generate much more compact layouts resulting in similar or even better circuit performance compared with the previous work.

Original languageEnglish
Article number6816125
Pages (from-to)879-892
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume33
Issue number6
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Analog layout
  • analog placement
  • current flow
  • current path
  • signal flow
  • slicing tree
  • symmetry

Fingerprint Dive into the research topics of 'Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement'. Together they form a unique fingerprint.

  • Cite this