Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

K. Tachi*, M. Cassé, S. Barraud, C. Dupré, A. Hubert, N. Vulliet, M. E. Faivre, C. Vizioz, C. Carabasse, V. Delaye, J. M. Hartmann, H. Iwai, S. Cristoloveanu, O. Faynot, T. Ernst

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (Leff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H2 anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

Original languageEnglish
Title of host publication2010 IEEE International Electron Devices Meeting, IEDM 2010
Pages34.4.1-34.4.4
DOIs
StatePublished - 2010
Event2010 IEEE International Electron Devices Meeting, IEDM 2010 - San Francisco, CA, United States
Duration: 6 Dec 20108 Dec 2010

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2010 IEEE International Electron Devices Meeting, IEDM 2010
CountryUnited States
CitySan Francisco, CA
Period6/12/108/12/10

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