Experimental studies on deep submicron CMOS scaling

K. Chen*, Chen-Ming Hu, P. Fang, A. Gupta, M. R. Lin, D. L. Wollesen

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

N- and surface channel p-MOSFETs and CMOS ring oscillators with channel lengths down to 0.2 μm and physical gate oxide thicknesses of 2.5 nm-5.8 nm were fabricated. The parasitic SD series resistance, threshold voltages, finite thickness of inversion layer including quantum and polysilicon gate depletion effects, drain saturation current, load capacitance of ring oscillator and ring oscillator speed were characterized at voltages from 1.5 to 3.3 V. The results confirmed the accuracy of the analytical models recently developed. The existence of an optimum gate oxide for given V gs , V th , R s and L eff is demonstrated from both the analytical model and the experimental data.

Original languageEnglish
Pages (from-to)816-820
Number of pages5
JournalSemiconductor Science and Technology
Volume13
Issue number7
DOIs
StatePublished - 1 Jul 1998

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