Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process

Tung Yang Chen*, Ming-Dou Ker, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

13 Scopus citations

Abstract

In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.

Original languageEnglish
Pages (from-to)35-38
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs
StatePublished - 1 Jan 1999
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 7 Jun 199910 Jun 1999

Fingerprint Dive into the research topics of 'Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process'. Together they form a unique fingerprint.

Cite this