In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.
|Number of pages||4|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|State||Published - 1 Jan 1999|
|Event||Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan|
Duration: 7 Jun 1999 → 10 Jun 1999