Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process

Tung Yang Chen; Ming-Dou Ker; Chung-Yu Wu

doi:10.1109/VTSA.1999.785993

Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process

Tung Yang Chen^*, Ming-Dou Ker, Chung-Yu Wu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.

Original language	English
Pages (from-to)	35-38
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.1999.785993
State	Published - 1 Jan 1999
Event	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 7 Jun 1999 → 10 Jun 1999

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title = "Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process",

abstract = "In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.",

author = "Chen, {Tung Yang} and Ming-Dou Ker and Chung-Yu Wu",

year = "1999",

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doi = "10.1109/VTSA.1999.785993",

language = "English",

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journal = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

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note = "null ; Conference date: 07-06-1999 Through 10-06-1999",

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TY - JOUR

T1 - Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process

AU - Chen, Tung Yang

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.

AB - In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.

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U2 - 10.1109/VTSA.1999.785993

DO - 10.1109/VTSA.1999.785993

M3 - Conference article

AN - SCOPUS:0032599280

SP - 35

EP - 38

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SN - 1524-766X

Y2 - 7 June 1999 through 10 June 1999

ER -

Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process

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