Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

Sheng Fu Hsu*, Ming-Dou Ker, Geeng Lih Lin, Yeh Ning Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.

Original languageEnglish
Title of host publication2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
Pages140-144
Number of pages5
DOIs
StatePublished - 1 Dec 2006
Event44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States
Duration: 26 Mar 200630 Mar 2006

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
CountryUnited States
CitySan Jose, CA
Period26/03/0630/03/06

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    Hsu, S. F., Ker, M-D., Lin, G. L., & Jou, Y. N. (2006). Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process. In 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual (pp. 140-144). [4017147] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2006.251206