Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Chemical Compounds

Engineering & Materials Science