Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have experimentally demonstrated fully suspended nanowire (NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm × 12.5 -nm); they exhibit a remarkable Ion-Ioff ratio of over 1010. This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S min of 39.22 mV/decade. A ZrO2 seed-layer is inserted under HfZr 1-x, Ox(HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (IG) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.

Original languageEnglish
Title of host publication2019 Silicon Nanoelectronics Workshop, SNW 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487024
DOIs
StatePublished - Jun 2019
Event24th Silicon Nanoelectronics Workshop, SNW 2019 - Kyoto, Japan
Duration: 9 Jun 201910 Jun 2019

Publication series

Name2019 Silicon Nanoelectronics Workshop, SNW 2019

Conference

Conference24th Silicon Nanoelectronics Workshop, SNW 2019
CountryJapan
CityKyoto
Period9/06/1910/06/19

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    Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y., & Chao, T. S. (2019). Experimental demonstration of performance enhancement of MFMIS and MFIS for 5-nm × 12.5-nm poly-Si nanowire gate-all-around negative capacitance FETs featuring seed-layer and PMA-free process. In 2019 Silicon Nanoelectronics Workshop, SNW 2019 [8782939] (2019 Silicon Nanoelectronics Workshop, SNW 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2019.8782939