Experimental 4 Mb CMOS EEPROM with a NAND structured cell

Yasuo Itoh*, Masaki Momodomi, Shirota Riichiro, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Koichi Toita, Satoshi Inoue, Fujio Masuoka

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

24 Scopus citations

Abstract

A 5-V-only CMOS 512k x 8 EEPROM (electrically erasable and programmable read-only memory), which achieves 104 cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structure cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor ensures selectivity; the second prevents the current from passing during programming operation. The current cell has one select transistor per bit. However, the NAND structure has only two select transistors per 8 bits; therefore it has only 1/4 select transistor and 1/16 contact hole per bit. Thus, the NAND structure can realize a smaller cell area than that of the current cell. For high-speed programming, a page mode is adopted. In read operation, address transition detection circuitry is used to precharge the bit lines and reset the read control circuitry. A summary of design characteristics is presented.

Original languageEnglish
Pages (from-to)134-135, 314
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume32
DOIs
StatePublished - 1 Dec 1989
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 15 Feb 198917 Feb 1989

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