TY - JOUR
T1 - Experimental 4 Mb CMOS EEPROM with a NAND structured cell
AU - Itoh, Yasuo
AU - Momodomi, Masaki
AU - Riichiro, Shirota
AU - Iwata, Yoshihisa
AU - Nakayama, Ryozo
AU - Kirisawa, Ryouhei
AU - Tanaka, Tomoharu
AU - Toita, Koichi
AU - Inoue, Satoshi
AU - Masuoka, Fujio
PY - 1989/12/1
Y1 - 1989/12/1
N2 - A 5-V-only CMOS 512k x 8 EEPROM (electrically erasable and programmable read-only memory), which achieves 104 cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structure cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor ensures selectivity; the second prevents the current from passing during programming operation. The current cell has one select transistor per bit. However, the NAND structure has only two select transistors per 8 bits; therefore it has only 1/4 select transistor and 1/16 contact hole per bit. Thus, the NAND structure can realize a smaller cell area than that of the current cell. For high-speed programming, a page mode is adopted. In read operation, address transition detection circuitry is used to precharge the bit lines and reset the read control circuitry. A summary of design characteristics is presented.
AB - A 5-V-only CMOS 512k x 8 EEPROM (electrically erasable and programmable read-only memory), which achieves 104 cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structure cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor ensures selectivity; the second prevents the current from passing during programming operation. The current cell has one select transistor per bit. However, the NAND structure has only two select transistors per 8 bits; therefore it has only 1/4 select transistor and 1/16 contact hole per bit. Thus, the NAND structure can realize a smaller cell area than that of the current cell. For high-speed programming, a page mode is adopted. In read operation, address transition detection circuitry is used to precharge the bit lines and reset the read control circuitry. A summary of design characteristics is presented.
UR - http://www.scopus.com/inward/record.url?scp=0024908025&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.1989.48209
DO - 10.1109/ISSCC.1989.48209
M3 - Conference article
AN - SCOPUS:0024908025
VL - 32
SP - 134-135, 314
JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SN - 0193-6530
Y2 - 15 February 1989 through 17 February 1989
ER -