Experimental 27 ns 1 Mb CMOS high-speed DRAM

S. Dhong; W. Henkels; N. Lu; R. Scheuerlein; G. Bronner; K. Kitamura; Y. Katayama; H. Niijima; T. Kirihata; R. Franch; Wei Hwang; M. Nishiwaki; F. Pesavento; T. Rajeevakumar; Y. Sakaue; Y. Suzuki; E. Yano

Experimental 27 ns 1 Mb CMOS high-speed DRAM

S. Dhong^*, W. Henkels, N. Lu, R. Scheuerlein, G. Bronner, K. Kitamura, Y. Katayama, H. Niijima, T. Kirihata, R. Franch, Wei Hwang, M. Nishiwaki, F. Pesavento, T. Rajeevakumar, Y. Sakaue, Y. Suzuki, E. Yano

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-V_DD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.

Original language	English
Pages	107-108
Number of pages	2
State	Published - 1 Dec 1989
Event	Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 25 May 1989 → 27 May 1989

Conference

Conference	Symposium on VLSI Circuits 1989
City	Kyoto, Japan
Period	25/05/89 → 27/05/89

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title = "Experimental 27 ns 1 Mb CMOS high-speed DRAM",

abstract = "The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-VDD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.",

author = "S. Dhong and W. Henkels and N. Lu and R. Scheuerlein and G. Bronner and K. Kitamura and Y. Katayama and H. Niijima and T. Kirihata and R. Franch and Wei Hwang and M. Nishiwaki and F. Pesavento and T. Rajeevakumar and Y. Sakaue and Y. Suzuki and E. Yano",

year = "1989",

month = dec,

day = "1",

language = "English",

pages = "107--108",

note = "null ; Conference date: 25-05-1989 Through 27-05-1989",

}

Experimental 27 ns 1 Mb CMOS high-speed DRAM. / Dhong, S.; Henkels, W.; Lu, N.; Scheuerlein, R.; Bronner, G.; Kitamura, K.; Katayama, Y.; Niijima, H.; Kirihata, T.; Franch, R.; Hwang, Wei; Nishiwaki, M.; Pesavento, F.; Rajeevakumar, T.; Sakaue, Y.; Suzuki, Y.; Yano, E.

1989. 107-108 Paper presented at Symposium on VLSI Circuits 1989, Kyoto, Japan, .

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Experimental 27 ns 1 Mb CMOS high-speed DRAM

AU - Dhong, S.

AU - Henkels, W.

AU - Lu, N.

AU - Scheuerlein, R.

AU - Bronner, G.

AU - Kitamura, K.

AU - Katayama, Y.

AU - Niijima, H.

AU - Kirihata, T.

AU - Franch, R.

AU - Hwang, Wei

AU - Nishiwaki, M.

AU - Pesavento, F.

AU - Rajeevakumar, T.

AU - Sakaue, Y.

AU - Suzuki, Y.

AU - Yano, E.

PY - 1989/12/1

Y1 - 1989/12/1

N2 - The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-VDD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.

AB - The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-VDD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.

UR - http://www.scopus.com/inward/record.url?scp=0024891292&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0024891292

SP - 107

EP - 108

Y2 - 25 May 1989 through 27 May 1989

ER -

Experimental 27 ns 1 Mb CMOS high-speed DRAM

Abstract

Conference

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