Experimental 27 ns 1 Mb CMOS high-speed DRAM

S. Dhong*, W. Henkels, N. Lu, R. Scheuerlein, G. Bronner, K. Kitamura, Y. Katayama, H. Niijima, T. Kirihata, R. Franch, Wei Hwang, M. Nishiwaki, F. Pesavento, T. Rajeevakumar, Y. Sakaue, Y. Suzuki, E. Yano

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-VDD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.

Original languageEnglish
Pages107-108
Number of pages2
StatePublished - 1 Dec 1989
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 25 May 198927 May 1989

Conference

ConferenceSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period25/05/8927/05/89

Fingerprint Dive into the research topics of 'Experimental 27 ns 1 Mb CMOS high-speed DRAM'. Together they form a unique fingerprint.

  • Cite this

    Dhong, S., Henkels, W., Lu, N., Scheuerlein, R., Bronner, G., Kitamura, K., Katayama, Y., Niijima, H., Kirihata, T., Franch, R., Hwang, W., Nishiwaki, M., Pesavento, F., Rajeevakumar, T., Sakaue, Y., Suzuki, Y., & Yano, E. (1989). Experimental 27 ns 1 Mb CMOS high-speed DRAM. 107-108. Paper presented at Symposium on VLSI Circuits 1989, Kyoto, Japan, .