The authors describe an experimental 256K-word by 4-b CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns was obtained. This performance was achieved by strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half-VDD sensing without dummy cells, and segmented I/O lines for faster I/O sensing. Unique wordline and bitline redundancy that does not adversely affect access and cycle times was implemented. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. A bitline margin test done by changing the bitline precharge voltage enhances the testability of the memory arrays.
|Number of pages||2|
|State||Published - 1 Dec 1989|
|Event||Symposium on VLSI Circuits 1989 - Kyoto, Japan|
Duration: 25 May 1989 → 27 May 1989
|Conference||Symposium on VLSI Circuits 1989|
|Period||25/05/89 → 27/05/89|