Expandable MDC-based FFT architecture and its generator for high-performance applications

Bu Ching Lin*, Yu Hsiang Wang, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Fast Fourier Transform (FFT) cores are extensively used in digital signal processing (DSP) applications like communication systems. Many pipelined FFT architectures optimized for different objectives have been proposed in past few decades. Though a fixed pipelined FFT architecture can generally provide good throughput at reasonable hardware cost, it may still fail to meet the performance demand for throughput-hungry design cases. In this paper, we propose an expandable MDC-based FFT architecture as well as the corresponding hardware design generator, which is capable of automatically producing an FFT core under a given throughput constraint. The experimental results show that the proposed methodology can generate smaller and power-efficient implementations than the existing foldable MDC-based FFT architecture.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2010
Pages188-192
Number of pages5
DOIs
StatePublished - 1 Dec 2010
Event23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
Duration: 27 Sep 201029 Sep 2010

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference23rd IEEE International SOC Conference, SOCC 2010
CountryUnited States
CityLas Vegas, NV
Period27/09/1029/09/10

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