Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test

Ming-Dou Ker*, Sheng Fu Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Different types of board-level noise filter networks are evaluated for their effectiveness to improve the immunity of CMOS ICs against transient-induced latchup (TLU) under system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the SCR test structures and the ring oscillator fabricated in a 0.25-μm CMOS technology. Some of such board-level solutions can be further integrated into the chip design to effectively improve TLU immunity of CMOS IC products.

Original languageEnglish
Title of host publication2005 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2005
StatePublished - 1 Dec 2005
Event2005 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2005 - Anaheim, CA, United States
Duration: 8 Sep 200516 Sep 2005

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Conference

Conference2005 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2005
CountryUnited States
CityAnaheim, CA
Period8/09/0516/09/05

Fingerprint Dive into the research topics of 'Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test'. Together they form a unique fingerprint.

Cite this