Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness

Chien Ju Chen, Yin Nien Chen, Ming Long Fan, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we comprehensively investigate the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-look-ahead adder (CLA) circuits operating in near-threshold region using atomistic 3D TCAD mixed-mode simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that at low operating voltage (< 0.3V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET even with the impacts of random variations. As the operating voltage decreases, the performance advantage of TFET CLA becomes more significant due to its better I on and C g, ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I off variability of TFET devices.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2325-2328
Number of pages4
ISBN (Electronic)9781479983919
DOIs
StatePublished - 27 Jul 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period24/05/1527/05/15

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