In this paper, we comprehensively investigate the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-look-ahead adder (CLA) circuits operating in near-threshold region using atomistic 3D TCAD mixed-mode simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that at low operating voltage (< 0.3V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET even with the impacts of random variations. As the operating voltage decreases, the performance advantage of TFET CLA becomes more significant due to its better I
and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I
variability of TFET devices.