Evaluation of sub-0.2 V high-speed low-power circuits using hetero-channel MOSFET and tunneling FET devices

Yin Nien Chen*, Ming Long Fan, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low VT hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at VDD=0.2V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.

Original languageEnglish
Article number6870502
Pages (from-to)3339-3347
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number12
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Hetero-channel MOSFET
  • high-speed
  • low-power
  • tunnel FET

Fingerprint Dive into the research topics of 'Evaluation of sub-0.2 V high-speed low-power circuits using hetero-channel MOSFET and tunneling FET devices'. Together they form a unique fingerprint.

Cite this