TY - GEN
T1 - Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices
AU - Hu, Vita Pi Ho
AU - Fan, Ming Long
AU - Su, Pin
AU - Chuang, Ching Te
PY - 2010/12/30
Y1 - 2010/12/30
N2 - This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = 1V, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors (PUAX-Asym.). We also show, for the first time, that as Vdd is reduced (e.g. < 0.6V), the effectiveness of using asymmetric source/drain-underlap access transistors to improve RSNM diminishes due to the worse electrostatic integrity caused by the underlap. At Vdd = 1V, the 6T PUAX-Asym. SRAM cell shows 20.5% improvement in RSNM, comparable WSNM, 10% degradation in "cell" Read access time and 36% improvement in Time-to-Write compared with the conventional 6T SRAM cell (Symm.). The PUAX-Asym. SRAM cell also shows adequate μRSNM/σRSNM and μWSNM/σWSNM at Vdd = 1V.
AB - This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = 1V, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors (PUAX-Asym.). We also show, for the first time, that as Vdd is reduced (e.g. < 0.6V), the effectiveness of using asymmetric source/drain-underlap access transistors to improve RSNM diminishes due to the worse electrostatic integrity caused by the underlap. At Vdd = 1V, the 6T PUAX-Asym. SRAM cell shows 20.5% improvement in RSNM, comparable WSNM, 10% degradation in "cell" Read access time and 36% improvement in Time-to-Write compared with the conventional 6T SRAM cell (Symm.). The PUAX-Asym. SRAM cell also shows adequate μRSNM/σRSNM and μWSNM/σWSNM at Vdd = 1V.
UR - http://www.scopus.com/inward/record.url?scp=78650529203&partnerID=8YFLogxK
U2 - 10.1109/SOI.2010.5641392
DO - 10.1109/SOI.2010.5641392
M3 - Conference contribution
AN - SCOPUS:78650529203
SN - 9781424491285
T3 - Proceedings - IEEE International SOI Conference
BT - 2010 IEEE International SOI Conference, SOI 2010
Y2 - 11 October 2010 through 14 October 2010
ER -