Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices

Vita Pi Ho Hu, Ming Long Fan, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = 1V, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors (PUAX-Asym.). We also show, for the first time, that as Vdd is reduced (e.g. < 0.6V), the effectiveness of using asymmetric source/drain-underlap access transistors to improve RSNM diminishes due to the worse electrostatic integrity caused by the underlap. At Vdd = 1V, the 6T PUAX-Asym. SRAM cell shows 20.5% improvement in RSNM, comparable WSNM, 10% degradation in "cell" Read access time and 36% improvement in Time-to-Write compared with the conventional 6T SRAM cell (Symm.). The PUAX-Asym. SRAM cell also shows adequate μRSNM/σRSNM and μWSNM/σWSNM at Vdd = 1V.

Original languageEnglish
Title of host publication2010 IEEE International SOI Conference, SOI 2010
DOIs
StatePublished - 30 Dec 2010
Event2010 IEEE International Silicon on Insulator Conference, SOI 2010 - San Diego, CA, United States
Duration: 11 Oct 201014 Oct 2010

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Conference

Conference2010 IEEE International Silicon on Insulator Conference, SOI 2010
CountryUnited States
CitySan Diego, CA
Period11/10/1014/10/10

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  • Cite this

    Hu, V. P. H., Fan, M. L., Su, P., & Chuang, C. T. (2010). Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices. In 2010 IEEE International SOI Conference, SOI 2010 [5641392] (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2010.5641392