Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Tse Ching Wu, Chien Ju Chen, Yin Nien Chen, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage C2MOS latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE International System on Chip Conference, SOCC 2015
EditorsKaran Bhatia, Thomas Buchner, Danella Zhao, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages339-344
Number of pages6
ISBN (Electronic)9781467390934
DOIs
StatePublished - 12 Feb 2016
Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
Duration: 8 Sep 201511 Sep 2015

Publication series

NameInternational System on Chip Conference
Volume2016-February
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference28th IEEE International System on Chip Conference, SOCC 2015
CountryChina
CityBeijing
Period8/09/1511/09/15

Keywords

  • FinFET
  • Verilog-A model
  • fin line-edge roughness
  • hybrid circuit
  • latch
  • tunneling FET
  • work function variation

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