Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor with Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications

Jing Neng Yao, Yueh Chin Lin, Heng-Tung Hsu, Kai Chun Yang, Hisang Hua Hsu, Simon M. Sze, Edward Yi Chang*

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 \times 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 \times 10^{-5} A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.

Original languageEnglish
Article number8404134
Pages (from-to)797-802
Number of pages6
JournalIEEE Journal of the Electron Devices Society
Volume6
DOIs
StatePublished - 4 Jul 2018

Keywords

  • E-mode
  • InAs
  • non-alloyed
  • sidewall etch

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