Estimation of process variation impact on DG-FinFET Device performance using Plackett-Burman Design of Experiment Method

ANChandorkar*, Sudhakar Mande, Hiroshi Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper studies various Double-Gate (DG) FinFET structures optimized for better "off state" and "on state" performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on Ion of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman Design of Experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET device's electrical performance.

Original languageEnglish
Title of host publicationICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages215-218
Number of pages4
DOIs
StatePublished - 2008
Event2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China
Duration: 20 Oct 200823 Oct 2008

Publication series

NameInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Conference

Conference2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
CountryChina
CityBeijing
Period20/10/0823/10/08

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