ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

Ming-Dou Ker*, Wei Jen Chang, Chang Tzu Wang, Wen Yi Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.

Original languageEnglish
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
StatePublished - 1 Dec 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 6 Feb 20069 Feb 2006

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period6/02/069/02/06

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    Ker, M-D., Chang, W. J., Wang, C. T., & Chen, W. Y. (2006). ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS. In 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers [1696284] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2006.1696284