ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

Ming-Dou Ker*, Hun Hsien Chang, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.

Original languageEnglish
Pages (from-to)543-546
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1995
EventProceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA
Duration: 10 Dec 199513 Dec 1995

Fingerprint Dive into the research topics of 'ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure'. Together they form a unique fingerprint.

Cite this