ESD protection design with stacked high-holding-voltage SCR for high-voltage pins in a battery-monitoring IC

Chia Tsen Dai, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticle

16 Scopus citations

Abstract

For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked high-holding-voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- μ 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress.

Original languageEnglish
Article number7446328
Pages (from-to)1996-2002
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume63
Issue number5
DOIs
StatePublished - 1 May 2016

Keywords

  • Electrostatic discharge (ESD)
  • holding voltage
  • latchup-free immunity
  • silicon-controlled rectifier (SCR).

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