ESD protection design with lateral DMOS transistor in 40-V BCD technology

Chang Tzu Wang*, Ming-Dou Ker, Tien Hao Tang, Kuan Cheng Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.

Original languageEnglish
Title of host publicationIPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs
StatePublished - 15 Sep 2010
Event17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore
Duration: 5 Jul 20109 Jul 2010

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
CountrySingapore
CitySingapore
Period5/07/109/07/10

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