ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Ming-Dou Ker, Chyh Yih Chang, Yi Shu Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 μm between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.

Original languageEnglish
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages234-238
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - 1 Jan 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: 25 Sep 200228 Sep 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Conference

Conference15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period25/09/0228/09/02

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  • Cite this

    Ker, M-D., Chang, C. Y., & Chang, Y. S. (2002). ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 234-238). [1158062] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158062