ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Ming-Dou Ker, Tung Yang Chen, Chung-Yu Wu, Hun Hsien Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.

Original languageEnglish
Title of host publicationProceedings - 12th Annual IEEE International ASIC/SOC Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages352-356
Number of pages5
ISBN (Electronic)0780356322, 9780780356320
DOIs
StatePublished - 1 Jan 1999
Event12th Annual IEEE International ASIC/SOC Conference - Washington, United States
Duration: 15 Sep 199918 Sep 1999

Publication series

NameProceedings - 12th Annual IEEE International ASIC/SOC Conference

Conference

Conference12th Annual IEEE International ASIC/SOC Conference
CountryUnited States
CityWashington
Period15/09/9918/09/99

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    Ker, M-D., Chen, T. Y., Wu, C-Y., & Chang, H. H. (1999). ESD protection design on analog pin with very low input capacitance for RF or current-mode applications. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 352-356). [806533] (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806533