ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu; Hun Hsien Chang

doi:10.1109/4.859509

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Ming-Dou Ker, Tung Yang Chen, Chung-Yu Wu, Hun Hsien Chang

Research output: Contribution to journal › Article › peer-review

59 Scopus citations

Abstract

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-raits clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approx. 1.0 pF (including the bond-pad capacitance) for high-frequency applications.

Original language	English
Pages (from-to)	1194-1199
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	35
Issue number	8
DOIs	https://doi.org/10.1109/4.859509
State	Published - 1 Aug 2000

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title = "ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications",

abstract = "An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-raits clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approx. 1.0 pF (including the bond-pad capacitance) for high-frequency applications.",

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AB - An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-raits clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approx. 1.0 pF (including the bond-pad capacitance) for high-frequency applications.

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