ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker, Tung Yang Chen, Chung Yu Win

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations

Abstract

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages754-757
Number of pages4
DOIs
StatePublished - 1 Dec 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 6 May 20019 May 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Conference

Conference2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period6/05/019/05/01

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