ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker*, T. Y. Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.

Original languageEnglish
Article number922347
Pages (from-to)IV754-IV757
Number of pages4
JournalMaterials Research Society Symposium - Proceedings
Volume626
StatePublished - Apr 2000
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 24 Apr 200027 Apr 2000

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