ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

Ming-Dou Ker*, Hsin Chyh Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-μ m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased ∼60% by this substrate-triggered design.

Original languageEnglish
Pages (from-to)44-53
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume52
Issue number1
DOIs
StatePublished - 1 Jan 2005

Keywords

  • Electrostatic discharge (ESD)
  • Mixed-voltage I/O
  • Stacked nMOS
  • Substrate-triggered technique

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