ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.
|Number of pages||4|
|State||Published - 1 Dec 2004|
|Event||Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan|
Duration: 5 Jul 2004 → 8 Jul 2004
|Conference||Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004|
|Period||5/07/04 → 8/07/04|