ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

Ming-Dou Ker*, Che Hao Chuang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations

Abstract

ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.

Original languageEnglish
Pages217-220
Number of pages4
StatePublished - 1 Dec 2004
EventProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan
Duration: 5 Jul 20048 Jul 2004

Conference

ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
CountryTaiwan
Period5/07/048/07/04

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