ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

Yuan Wen Hsiao*, Ming-Dou Ker, Po Yen Chiu, Chun Huang, Yuh Kuang Tseng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages277-280
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
Duration: 26 Sep 200729 Sep 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
CountryTaiwan
CityHsinchu
Period26/09/0729/09/07

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    Hsiao, Y. W., Ker, M-D., Chiu, P. Y., Huang, C., & Tseng, Y. K. (2007). ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. In Proceedings - 20th Anniversary IEEE International SOC Conference (pp. 277-280). [4545474] (Proceedings - 20th Anniversary IEEE International SOC Conference). https://doi.org/10.1109/SOCC.2007.4545474