ESD protection design for 1- To 10-GHz distributed amplifier in CMOS technology

Ming-Dou Ker*, Yuan Wen Hsiao, Bing Jye Kuo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

20 Scopus citations

Abstract

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-μm CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7±1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9±1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.

Original languageEnglish
Pages (from-to)2672-2681
Number of pages10
JournalIEEE Transactions on Microwave Theory and Techniques
Volume53
Issue number9
DOIs
StatePublished - 1 Sep 2005

Keywords

  • Decreasing-sized distributed ESD (DS-DESD)
  • Distributed amplifier (DA)
  • Electrostatic discharge (ESd)
  • Equal-sized distributed ESD (ES-DESD)
  • Resistive ladder

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