ESD protection design and verification in a 0.35-μm CMOS ASIC library

Ming-Dou Ker, Hsin Chin Jiang, Jeng Jie Peng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.

Original languageEnglish
Title of host publicationProceedings - 12th Annual IEEE International ASIC/SOC Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages262-266
Number of pages5
ISBN (Electronic)0780356322, 9780780356320
DOIs
StatePublished - 1 Jan 1999
Event12th Annual IEEE International ASIC/SOC Conference - Washington, United States
Duration: 15 Sep 199918 Sep 1999

Publication series

NameProceedings - 12th Annual IEEE International ASIC/SOC Conference

Conference

Conference12th Annual IEEE International ASIC/SOC Conference
CountryUnited States
CityWashington
Period15/09/9918/09/99

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  • Cite this

    Ker, M-D., Jiang, H. C., & Peng, J. J. (1999). ESD protection design and verification in a 0.35-μm CMOS ASIC library. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 262-266). [806516] (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806516