ESD protection consideration in nanoscale CMOS technology

Ming-Dou Ker*, Chun Yu Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.

Original languageEnglish
Title of host publication2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Pages720-723
Number of pages4
DOIs
StatePublished - 1 Dec 2011
Event2011 11th IEEE International Conference on Nanotechnology, NANO 2011 - Portland, OR, United States
Duration: 15 Aug 201119 Aug 2011

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference2011 11th IEEE International Conference on Nanotechnology, NANO 2011
CountryUnited States
CityPortland, OR
Period15/08/1119/08/11

Keywords

  • CMOS
  • electrostatic discharge (ESD)
  • on-chip ESD protection

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