ESD-induced latchup-like failure in a touch panel control IC

Ming-Dou Ker, Po Yen Chiu, Wuu Trong Shieh, Chun Chi Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.

Original languageEnglish
Title of host publication24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-5
Number of pages5
ISBN (Electronic)9781538617793
DOIs
StatePublished - 5 Oct 2017
Event24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 - Chengdu, China
Duration: 4 Jul 20177 Jul 2017

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2017-July

Conference

Conference24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
CountryChina
CityChengdu
Period4/07/177/07/17

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