ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker*, C. H. Chuang

*Corresponding author for this work

Research output: Contribution to conferencePaper

22 Scopus citations

Abstract

The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

Original languageEnglish
Pages85-90
Number of pages6
StatePublished - 1 Jan 2001
Event8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
Duration: 9 Jul 200113 Jul 2001

Conference

Conference8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
CountrySingapore
CitySingapure
Period9/07/0113/07/01

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    Ker, M-D., & Chuang, C. H. (2001). ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration. 85-90. Paper presented at 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapure, Singapore.