ESD failure mechanisms of analog I/O cells in 0.18-μm CMOS technology

Ming-Dou Ker*, Shih Hung Chen, Che Hao Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

Different electrostatic discharge (ESD) protection schemes have been investigated to und the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-μm 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-μm CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.

Original languageEnglish
Pages (from-to)102-111
Number of pages10
JournalIEEE Transactions on Device and Materials Reliability
Volume6
Issue number1
DOIs
StatePublished - 1 Mar 2006

Keywords

  • Analog I/O
  • Electrostatic discharge (ESD)
  • Failure mechanism
  • Input/output (I/O) cell
  • Power-rail ESD clamp device

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