This paper describes a novel embedded subranging type 10-bit 5 MHz CMOS error correction free analog-to-digital converter (ADC). The new structure solves the problem that the number of comparators in the fine ADC is increased as the number of bits is increased. The power dissipation of the comparator is explored and an innovative bisection MSB comparator is designed to further reduce power consumption and chip area of the new ADC. According to the simulation results, the new ADC can achieve 10-bit resolution and 2 MHz input bandwidth at a sampling rate of 5 MHz using 5V 0.8 um CMOS process. The active die size is 1.4×2.2 mm 2 and the power dissipation is 175 mW at 5V.
|Number of pages||4|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - 1 Dec 1995|
|Event||Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA|
Duration: 18 Sep 1995 → 22 Sep 1995