Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory

S. H. Ku, T. W. Lin, C. H. Cheng, C. W. Lee, Ti Wen Chen, Wen Jer Tsai, T. C. Lu, W. P. Lu, K. C. Chen, Ta-Hui Wang, Chih Yuan Lu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR 2 ) is proposed and validated by BPT. The advantage of MTVR 2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR2 is also evaluated.

Original languageEnglish
Title of host publication2018 IEEE 10th International Memory Workshop, IMW 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538652473
DOIs
StatePublished - 19 Jun 2018
Event10th IEEE International Memory Workshop, IMW 2018 - Kyoto, Japan
Duration: 13 May 201816 May 2018

Publication series

Name2018 IEEE 10th International Memory Workshop, IMW 2018

Conference

Conference10th IEEE International Memory Workshop, IMW 2018
CountryJapan
CityKyoto
Period13/05/1816/05/18

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