Enhanced stability of thin film transistors with double-stacked amorphous IWO/IWO:N channel layer

Dong Lin, Shubin Pi, Jianwen Yang, Nidhi Tiwari, Jinhua Ren, Qun Zhang*, Po-Tsun Liu, Han Ping Shieh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

In this work, bottom-gate top-contact thin film transistors with double-stacked amorphous IWO/IWO:N channel layer were fabricated. Herein, amorphous IWO and N-doped IWO were deposited as front and back channel layers, respectively, by radio-frequency magnetron sputtering. The electrical characteristics of the bi-layer-channel thin film transistors (TFTs) were examined and compared with those of single-layer-channel (i.e., amorphous IWO or IWO:N) TFTs. It was demonstrated to exhibit a high mobility of 27.2 cm2 V-1 s-1 and an on/off current ratio of 107. Compared to the single peers, bi-layer a-IWO/IWO:N TFTs showed smaller hysteresis and higher stability under negative bias stress and negative bias temperature stress. The enhanced performance could be attributed to its unique double-stacked channel configuration, which successfully combined the merits of the TFTs with IWO and IWO:N channels. The underlying IWO thin film provided percolation paths for electron transport, meanwhile, the top IWO:N layer reduced the bulk trap densities. In addition, the IWO channel/gate insulator interface had reduced defects, and IWO:N back channel surface was insensitive to the ambient atmosphere. Overall, the proposed bi-layer a-IWO/IWO:N TFTs show potential for practical applications due to its possibly long-term serviceability.

Original languageEnglish
Article number065001
JournalSemiconductor Science and Technology
Volume33
Issue number6
DOIs
StatePublished - Jun 2018

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