Enhanced planar poly-Si TFT EEPROM cell for system on panel applications

Po-Tsun Liu; C. S. Huang; C. W. Chen

doi:10.1149/1.2739214

Enhanced planar poly-Si TFT EEPROM cell for system on panel applications

Po-Tsun Liu^*, C. S. Huang, C. W. Chen

^*Corresponding author for this work

National Chiao Tung University

Research output: Contribution to journal › Article

7 Scopus citations

Abstract

In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.

Original language	English
Journal	Electrochemical and Solid-State Letters
Volume	10
Issue number	8
DOIs	https://doi.org/10.1149/1.2739214
State	Published - 20 Jun 2007

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AB - In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.

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