Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs

Chih-Yu Hsu, Chien-Chih Lee, Yi-Tang Lin, Chen-Yu Hsieh, Ming-Jer Chen

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.
Original languageAmerican English
Pages (from-to)1667-1673
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume56
Issue number8
DOIs
StatePublished - Aug 2009

Keywords

  • Layout; mechanical stress; MOSFET; piezoresistance; shallow trench isolation (STI); tunneling

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