Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress

Kow-Ming Chang, Hung Chung Yuan Hung Chung, Ming Lin Gin Ming Lin, Gun Deng Chi Gun Deng, Hong Lin Jian Hong Lin

Research output: Contribution to journalArticle

26 Scopus citations

Abstract

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (Gm max) in static stress, Gm max in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: 1) breaking of weak bonds and 2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation.

Original languageEnglish
Pages (from-to)475-477
Number of pages3
JournalIEEE Electron Device Letters
Volume22
Issue number10
DOIs
StatePublished - 1 Oct 2001

Keywords

  • Channel shortening effect
  • Intra-grain bulk states
  • Polysilicon thin-film transistors (poly-Si TFTs)
  • Tail states
  • Transconductance (G)

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    Chang, K-M., Yuan Hung Chung, H. C., Gin Ming Lin, M. L., Chi Gun Deng, G. D., & Jian Hong Lin, H. L. (2001). Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress. IEEE Electron Device Letters, 22(10), 475-477. https://doi.org/10.1109/55.954916