Engineering negative differential resistance in NCFETs for analog applications

Harshit Agarwal*, Pragya Kushwaha, Juan Pablo Duarte, Yen Kai Lin, Angada B. Sachid, Ming Yen Kao, Huan Lin Chang, Sayeef Salahuddin, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

31 Scopus citations


In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing Vds in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance (gds) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce gds degradation in short-channel devices. Small and positive gds is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V Vdd is used as the baseline device in this paper.

Original languageEnglish
Pages (from-to)2033-2039
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number5
StatePublished - 1 May 2018


  • Analog applications
  • negative capacitance field-effect transistor (NCFET)
  • negative differential resistance (NDR)
  • sub-60 mv/decade

Fingerprint Dive into the research topics of 'Engineering negative differential resistance in NCFETs for analog applications'. Together they form a unique fingerprint.

Cite this