Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement

Yu Chien Chiu, Chun-Hu Cheng, Guan Lin Liou, Chun-Yen Chang

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
Original languageEnglish
Pages (from-to)3498-3501
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume64
Issue number8
DOIs
StatePublished - Aug 2017

Keywords

  • Charge trpapping; ferroelectric; multilevel; nonvolatile memory
  • SPEED; RAM

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