Energy-efficient techniques for circuit design in network-on-chip platforms

Po-Tsang Huang*, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Advanced network-on-chip (NOC) designs using nano-scale technologies face a number of challenges, especially for great amount of energy consumption in switch fabrics and link wires. In this paper, some energy-efficient techniques are presented for circuit design in network-on-chip platforms, including low-power and variation-tolerant link wires, adaptive congestion-aware routing and asynchronous two-level FIFO buffers. Energy-efficient and reliable link wires are provided by a novel self-calibrated low-power coding and voltage scaling interconnection architecture. This approach makes the NoC applications tolerant of transient malfunctions and realizes energy efficiency. Additionally, an adaptive congestion-aware routing is proposed to reduce the average latencies by avoiding the congestion conditions and distributed hotspots. Moreover, an asynchronous two-level FIFO buffer can reduce energy consumption compared with that of synchronous two-level FIFO buffers and conventional asynchronous output buffers.

Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages305-310
Number of pages6
DOIs
StatePublished - 20 Sep 2010
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 21 Jun 201023 Jun 2010

Publication series

Name1st International Conference on Green Circuits and Systems, ICGCS 2010

Conference

Conference1st International Conference on Green Circuits and Systems, ICGCS 2010
CountryChina
CityShanghai
Period21/06/1023/06/10

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