Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

Yung Chia Lin, Yi-Ping You, Chung Wen Huang, Jenq Kuen Lee*, Wei Kuan Shih, Ting Ting Hwang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

Dynamic voltage scaling (DVS) and power gating (PG) have become mainstream technologies for low-power optimization in recent years. One issue that remains to be solved is integrating these techniques in correlated domains operating with multiple voltages. This article addresses the problem of power-aware task scheduling on a scalable cryptographic processor that is designed as a heterogeneous and distributed system-on-a-chip, with the aim of effectively integrating DVS, PG, and the scheduling of resources in multiple voltage domains (MVD) to achieve low energy consumption. Our approach uses an analytic model as the basis for estimating the performance and energy requirements between different domains and addressing the scheduling issues for correlated resources in systems. We also present the results of performance and energy simulations from transaction-level models of our security processors in a variety of system configurations. The prototype experiments show that our proposed methods yield significant energy reductions. The proposed techniques will be useful for implementing DVS and PG in domains with multiple correlated resources.

Original languageEnglish
Pages (from-to)201-223
Number of pages23
JournalJournal of Supercomputing
Volume42
Issue number2
DOIs
StatePublished - 1 Nov 2007

Keywords

  • Dynamic voltage scaling
  • Parallel processing
  • Power gating
  • Power management
  • Scheduling
  • Security processor

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