Enabling compiler flow for embedded VLIW DSP Processors with Distributed Register Files

Chung Kai Chen*, Ling Hua Tseng, Shih Chang Chen, Young Jia Lin, Yi-Ping You, Chia Han Lu, Jenq Kuen Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.

Original languageEnglish
Pages (from-to)146-148
Number of pages3
JournalACM SIGPLAN Notices
Volume42
Issue number7
DOIs
StatePublished - 1 Jul 2007

Keywords

  • Distributed register files
  • Embedded VLIW DSP compilers
  • Software pipelining

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