Enabling circuit design using FinFETs through close ecosystem collaboration

Bing J. Sheu, Chih Sheng Chang, Yen Huei Chen, Ken Wang, Kuo Ji Chen, Yung Chow Peng, Li Chun Tien, Ming Hsiang Song, Cliff Hou, Jack Yuan Chen Sun, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes key issues in enabling circuit design using FinFETs and how to address them effectively.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
StatePublished - 9 Sep 2013
Event2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
Duration: 11 Jun 201313 Jun 2013

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2013 Symposium on VLSI Technology, VLSIT 2013
CountryJapan
CityKyoto
Period11/06/1313/06/13

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  • Cite this

    Sheu, B. J., Chang, C. S., Chen, Y. H., Wang, K., Chen, K. J., Peng, Y. C., Tien, L. C., Song, M. H., Hou, C., Sun, J. Y. C., & Hu, C-M. (2013). Enabling circuit design using FinFETs through close ecosystem collaboration. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers [6576615] (Digest of Technical Papers - Symposium on VLSI Technology).