Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes key issues in enabling circuit design using FinFETs and how to address them effectively.
|Title of host publication||2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers|
|State||Published - 17 Sep 2013|
|Event||2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan|
Duration: 12 Jun 2013 → 14 Jun 2013
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||2013 Symposium on VLSI Circuits, VLSIC 2013|
|Period||12/06/13 → 14/06/13|